In order to meet the requirements for digital chips having more functions and higher performance, a processor core, a plurality of multimedia modules, and various peripheral equipment modules are integrated in a single-chip application processor. Therefore, a plurality of circuit modules are usually integrated in a processor, and the number of gates included in the processor increases to several tens of millions or more. Since the circuit modules in a chip use different clock sources, there are many asynchronous reset circuit modules that are required to be tested to ascertain whether a timing violation occurs during a post-design operation (e.g., during a timing closure).
In more detail, when a chip is tested, a plurality of circuit modules in the chip may be reset in response to one or more reset signals. The reset signals may be at a high level or low level. When high level (or low level) reset signals are received, the circuit modules may be reset. If a rising edge (or a falling edge) of a clock signal input with respect to a circuit module occurs at or near a point in time when the circuit module receives a reset signal, the reset signal may not be accurately captured by the circuit module. If the reset signal is not accurately captured by the circuit module, a timing violation may occur, which may cause instability within the circuit module and may cause a failure in the test of the circuit module. Therefore, in the related art, a method of synchronizing a reset signal with a clock signal so as to maintain an interval between a time when the reset signal releases and a time when a rising edge (or a falling edge) of the clock signal occurs is proposed.
FIG. 1 is a diagram illustrating a circuit used for synchronizing a reset signal and a clock signal according to the related art, and FIG. 2 is a timing diagram of the circuit of FIG. 1.
Referring to FIGS. 1 and 2, a reset synchronizer 10 includes a first D flip-flop 11 and a second D flip-flop 12. A clock signal CLK drives first D flip-flop 11 (for example, via one or more buffers) and second D flip-flop 12. A pull up signal PULL-UP or a pull down signal (not shown) is supplied to first D flip-flop 11. An external circuit 20 may include flip-flops, logic devices, memory device, and/or other types of circuits. The clock signal CLK also drives the external circuit 20 (again, for example, via one or more buffers).
As shown in FIG. 1, a reset signal RESET for resetting the external circuit 20 is not directly supplied to the external circuit 20 but instead is supplied to reset synchronizer 10. The reset signal RESET is converted into an inverted reset signal RESET_n and the inverted reset signal RESET_n is supplied to the first D flip-flop 11 and the second D flip-flop 12. Reset synchronizer 10 outputs a synchronized reset signal RESET_n′, which is synchronized with the clock signal CLK, according the inverted reset signal RESET_n and the clock signal CLK. As illustrated in FIG. 2, a sufficient interval is maintained between a release time of the synchronized reset signal RESET_n′ and a rising edge of the clock signal CLK, so that a timing violation may be prevented. A violation window is also illustrated in FIG. 2. If a release time of a reset signal supplied to external circuit 20 is within the violation window, a timing violation may occur in external circuit 20.
However, in the circuit as illustrated in FIG. 1, the clock signal CLK is supplied while the reset signal RESET_n′ is supplied to external circuit 20. Therefore, during a post-design operation, for example, during a timing closure, a specialized Post-Static Timing Analysis (Post-STA) is required for each module including the conventional circuit shown in FIG. 1, so as to determine whether a sufficient interval is maintained between the release time of the synchronized reset signal RESET_n′ and the rising edge of the clock signal CLK.